Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

-- On Dec 15 2004 at 18:14, Shalom.Bresticker@freescale.com sent a message:
> To: sharp@cadence.com, sv-bc@eda.org
> Subject: "Re: [sv-bc] Errata: variable initializers don't match
> Verilog-2001"
>
> ... 1364-2001 5.4.2 says, "At any time while evaluating a
> behavioral statement, the simulator may suspend execution and place
> the partially completed event as a pending active event on the
> event queue. The effect of this is to allow the interleaving of
> process execution."

> I did not see a statement in SV that contradicts that. So an
> initial or always block might be started, then suspended, then an
> always_comb executed, then the initial or always block continued.
> But that is a digression.)

This particular digression is quite pertinate to the task
"countSlaves", on page 296 of SystemVerilog3.1a, in section 19.6.4,
"An example of multiple task exports"

Basically the example shows how the definition of a task in an
interface as "extern forkjoin" causes an invocation of that task to
call the task concurrently for each instance of the interface, in a
forkjoin block, as follows:

fork
 top.mem1.a.countSlaves;
 top.mem1.b.countSlaves;
join

where countSlaves is implemented as:

task a.countSlaves();
  a.slaves++;
endtask

There is a write-read race here; the rule in section 5.4.2 would allow
a conforming simulator to result in a value for a.slaves of either 1
or 2, by my reckoning.

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