Re: [sv-bc] Comments on issue 254 (aggregate expressions)

I agree with Steven.

It is also important to understand that many tools do depend on the declared
port direction and do not ignore it.
E.g., synthesis tools.
If you declare a direction wrong, you may get erroneous results.

Shalom

Steven Sharp wrote:

> I believe that Brad has overstated some things in discussing this issue.
> He has said that "input" and "output" on port declarations are just
> comments, and have no effect on the actual port direction. This is an
> overstatement.
>
> If a port undergoes port-collapsing (see 12.3.10 of IEEE Std 1364-2001),
> then it effectively becomes inout, regardless of how it was declared. In
> this case, the declared port direction becomes irrelevant.
>
> (Many users have relied on this behavior in Verilog-XL to "fix" incorrectly
> declared port directions. Apparently some people came to believe that the
> tool is deliberately "fixing" an incorrectly declared direction in cases
> where it has "detected" that it is wrong. In fact, Verilog-XL is simply
> collapsing the ports for its own reasons (mainly speed), independent of what
> direction it was declared and without "detecting" whether it was right or
> wrong. This misunderstanding led to the insertion of a note in 12.3.8,
> vaguely requiring implementations to "fix" incorrect port directions, to
> try to match what Verilog-XL appeared to be doing.)
>
> If a port does not get port-collapsed, then the port direction *does*
> matter. Consider the following example:
>
> module mymod (input wire [31:0] iport, output wire [31:0] oport);
> assign iport = oport;
> endmodule
>
> module top;
> mymod m(.iport(a+b), .oport(a+b));
> endmodule
>
> The expressions "a+b" cannot be port-collapsed, so they will be treated
> as continuous assignments. The connection to iport is legal, since it
> is an input port. It doesn't matter that it appears to be used as an
> output inside mymod. It is declared as an input port, and it is treated
> as an input port. There is a continuous assignment through the input port
> from "a+b" to iport, and it is also driven by the continuous assignment
> inside mymod, so the wire iport has two drivers.
>
> The connection to oport is illegal, since it is an output port. It doesn't
> matter that it appears to be used as an input inside mymod. It is declared
> as an output port, and it is treated as an output port. Since the port
> cannot be collapsed, it is treated as a continuous assignment through the
> output port to the port expression. The port expression "a+b" is not a
> legal left-hand-side of a continuous assignment. Therefore this is an
> error.
>
> I'm not sure exactly how this affects the "correspondence expression"
> proposal. However, if that proposal is based on the incorrect assumption
> that port directions are just comments and will always be adjusted to
> make the connections legal, then that proposal is faulty.
>
> Steven Sharp
> sharp@cadence.com

--
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                     Cell: +972 50 5441478
[ ]Freescale Internal Use Only      [ ]Freescale Confidential Proprietary