[sv-bc] Comments on Mantis #254

I though I would write down my comments on why I am against the proposal
to change the aggregate constructor syntax for today's SystemVerilog-BC
meeting at 10am

The issue is how the concat braces {}, are overloaded in SystemVerilog
as both a concatenation operator and array/struct constructor.

I.e.

reg [7:0] A; // a 7-bit vector

reg B[1:2][0:3] a 2 X4 1-bit array

reg a,b,c,d,e,f,g,h;

A = {a,b,c,d,e,f,g,h); // a concatenation

B = {{a,b,c,d},{e,f,g,h}}; an array constructor

The current proposal would either change the constructor to either a
different set of braces, like [[a,b,c,d],[h,I,j,k]], or the currently
preferred, require a ' mark in front of the first { like
'{'{a,b,c,d,'{e,f,g,h}}. This would also apply to queue and string
constructors.

 I am against this change because

1. I think this is a natural use of polymorphism; especially for
constructing queues and strings. The concatenation operator fits well
with aggregate queues and strings
2. This is a backward incompatible change of SV that has been
implemented in at least VCS and Modelsim for well over a year. By the
time this gets implemented and in users hands might be another year.
3. As a variable initializer, this creates yet another difference
from C.

I would rather we worked on creating clearing up the rules to remove
any ambiguities in the current spec than change the syntax

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office: 408 487-7206
Cell: 510 589-2625

 
Received on Tue Feb 1 09:18:38 2005