[sv-bc] inconsistency on port connections type rules

I found some inconsistency and need for clarifying the port connection rules

with respect to type compatibility sub-classifications.
 
Type compatibility in section 5.9  is categorized as either:
  type matching
  type equivalence
  type assignment compatibility
  type casting compatibility.
  type incompatible.
The first category provides the stricter type checking, type equivalent is
less stricter and 
type assignment compatibility is even less strict. Typically type assignment
compatibility adds
implicit cast to the type equivalence.
 
Chapter 19 of the last draft has different rules for regular port
connections (19.12), 
.name port connections (19.11.3) and .* port connections (19.11.4)
 
Regular Verilog 2001 allowed the ports to be connected if they were
assignment port
compatible.
I think that the .name, .* should be changed to require type assignment
compatibility.
 
In systemVerilog, extern module declaration ports must have port type
equivalence with the actual module
port types.
in 19.11.3 SystemVerilog implicit .name port connection requires type
equivalence on 
the port connected with the .name and also list some exceptions:
 
"A .port_identifier port connection is semantically equivalent to the named
port connection 

.port_identifier(name) port connection with the following exceptions:

- The identifier referenced by .port_identifier shall not create an implicit
wire declaration.

- It shall be illegal for a .port_identifier port connection to create an
implicit cast. This includes truncation or

padding.

- A conversion between a 2-state and 4-state type of the same bit length is
a legitimate cast.

- It shall be an error if a .port_identifier port connection between two
dissimilar net types would generate a

warning message as required by the Verilog standard."

I don't understand the need for type equivalence neither why we have these
exceptions. 

I don't see why we have the exception #2 but we allow 2 state to 4 state
implicit cast...

I cannot understand the last exception. What are two dissimilar net types?
Are we talking

about a size mismatch which would have been generated it it had been a
normal named port connection?

This is turned into an error for a .name connection?

Additionally the text should instead say 

"equivalent to the named port connection .port_identifier(port_identifier)"

Similarly there is type equivalent requirement for .* port connections as
described in 19.11.4

The spec also says that .* is semantically equivalent to a default .name
port connection for

every port:

"An implicit .* port connection is semantically equivalent to a default
.name port connection for every port

declared in the instantiated module. A named port connection can be mixed
with a .* connection to override the

port connection to a different expression or to leave the port unconnected."

  
In 19.12 the port connection rules are described and they require type
assignment compatibility.
"SystemVerilog extends Verilog port connections by making values of all data
types on variables and nets available 

to pass through ports. It does this by allowing both sides of a port
connection to have assignment compatible

data types, and by allowing continuous assignments to variables."

In 19.12.1 the variable port connection requires  type compatibility. This
wording is insufficient as type
compatibility has been further sub-classified. 
Ex:
"- An input port can be connected to any expression of a compatible data
type."
 
Same issue with 19.12.2 for net port conenction rules.
Ex:
"An output can be connected to a net or variable (or a concatenation of nets
or variables) of a compatible data type."
 
Section 19.12.3 is in fact is in contradiction with .name and .*
I belive that this seciton should appear ahead of the others. I also believe
that we 
should make .name and .* behave like normal port connections with assignment
type compatibility rules.
 
"19.12.4 Compatible port types 

The same rules are used for compatible port types as for assignment
compatibility. SystemVerilog does not

change any of the other port connection compatibility rules."

Section 19.12.5 unpacked array ports and array of instances also talks about
type matching.

"If the size and type of the port connection match the size and type of a
single instance port, the connection shall

be made to each instance in an array of instances."

Shouldn't this be changed to if the type of the port connection is
assignment compatible with

the type of the instance port...: