[sv-bc] FW: BOUNCE sv-bc@eda.org: Non-member submission from ["Rohit K. Jain" <rohit_jain@mentorg.com>]

>From: "Rohit K. Jain" <rohit_jain@mentorg.com>
>To: sv-bc@server.eda.org
>Subject: Issue in determining signedness of Array
>
>Hi,
>
>I have query on a case mentioned below, for which rules 
>doesn't seem clear.
>can someone please clarify.
>
>
>1)
>Consider the following example :
>
>typedef reg signed [7:0] xx;
>xx  [1:0]  temp ;
>
>always
>begin
>
>temp = '1;
>a1 = temp;  // signed or unsigned RHS??
>a1 = temp[0]; // signed
>a1 = temp[0][1]; // unsigned
>
>end
>
>
>LRM 4.2 says :
>If a packed array is declared as signed, then the array viewed as a 
>single vector shall be signed. The individual elements of the 
>array are 
>unsigned unless they are of a named type declared as signed. A 
>part-select of a packed array shall be unsigned.
>
>In the above example, what is signedness of packed array 
>'temp', when it 
>is viewed as single vector?
>
>Since it is not defined explicitly to be signed, and its element is 
>defined as named type signed.
>
>'temp' should be treated as unsigned, and its element i.e. temp[0] 
>should be treated as signed?
>
>OR
>
>'temp' should be treated as signed because its element type is signed?
>
>
>2)
>typedef reg [7:0] xx;
>xx  signed [1:0]  temp ;  // illegal
>
>If user intends to create a signed packed array using named type 
>element, how can it be achieved?
>
>
>Regards
>Rohit