Re: [sv-bc] Serious issue with default expressions for task and function arguments

>I suspect that some people would object to requiring functions
>to be pure within interfaces

Yes, indeed, people would object to disallowing void methods
in interfaces.

An interface method is in an interface instance, just as
a Verilog-1995 function is in a module instance.  It cannot
be referred to from outside that interface except via an
hierarchical reference.  The scoping in Verilog is static. 
The scoping in SystemVerilog is static.

It's perfectly reasonable for modports to name only the methods.
By using this API style, the signals in the interface stay hidden.
An advantage is that, combined with generic interface ports, it makes
it easier to explore various bus possibilities without recoding.
Given another interface that implements the same bus API, just change
the single interface instantiation in $root, and you're good to go. 

I don't understand the controversy.  Static scoping, information
hiding, ...  These are not controversial concepts. 

-- Brad