Re: [sv-bc] Serious issue with default expressions for task and function arguments

Cool -- so you agree that it is "obvious" that always_comb
should be sensitive to implicitly referenced interface
items via modport functions?  I'd certainly be happy with that
since it is consistent with my view and with the view that binding
happens in  the context of definition and no other naming in the
context of use interferes.  If we can all agree to that (which
I would), I'd be happy.

Gord.


Brad Pierce wrote:

>>I suspect that some people would object to requiring functions
>>to be pure within interfaces
> 
> 
> Yes, indeed, people would object to disallowing void methods
> in interfaces.
> 
> An interface method is in an interface instance, just as
> a Verilog-1995 function is in a module instance.  It cannot
> be referred to from outside that interface except via an
> hierarchical reference.  The scoping in Verilog is static. 
> The scoping in SystemVerilog is static.
> 
> It's perfectly reasonable for modports to name only the methods.
> By using this API style, the signals in the interface stay hidden.
> An advantage is that, combined with generic interface ports, it makes
> it easier to explore various bus possibilities without recoding.
> Given another interface that implements the same bus API, just change
> the single interface instantiation in $root, and you're good to go. 
> 
> I don't understand the controversy.  Static scoping, information
> hiding, ...  These are not controversial concepts. 
> 
> -- Brad
> 
> 

-- 
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Gordon Vreugdenhil,  Staff Engineer               503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com