[sv-bc] Operations allowed on ref arguments?

The LRM does not say what operations are allowed on ref arguments.  It
can be assumed that they can be read or written, but Verilog has a lot
of other operations that can be performed on variables.  For example,
they can be waited on in wait or event control statements, and they can
be assigned with nonblocking assignments, procedural continuous assignments
and forces.  Which of these operations are allowed for ref arguments?

Note that allowing some of these would create problems.  It is possible
to pass dynamic objects (and parts of dynamic objects) and automatic
variables by reference.  But according to 6.6, it is illegal to assign to
these objects using nonblocking assignments or continuous assignments
(which I assume actually refers to procedural continuous assignments and
forces).  If these operations are allowed on ref arguments, it could
violate the restrictions in 6.6.

Steven Sharp
sharp@cadence.com