[sv-bc] overiding the port of task

task t1 (output x);
  int x = 0;
 endtask

In the above example there is a error which can be classified into two 
categories

1. The port output x  has been declared in ANSI style and int x =0  is 
declared in task body
    in non  ANSI style, if int x =0 is not overriding the output port 
type then it should give
    an error for redeclaration of x. As there is no reference in LRM for 
overriding ANSI
     port by Non-ANSI port.

2.  If it is overriding the output port, then as per LRM output port 
cannot have default
     arguments,

Whether it is a positive testcase or not. If it is a negative testcase 
then what kind of
  error should be reported.

Thanks
Rakesh