Re: [sv-bc] overiding the port of task

Rakesh,

This is also a Verilog-2001 issue, not just a SystemVerilog issue.
See, for example,

   http://www.boyd.com/1364_btf/report/full_pr/227.html

For an archive of recent mail on the Verilog reflectors,
see

   http://www.boyd.com/1364_btf/archives.shtml

especially,

   http://boydtechinc.com/etf/archive/date.html


-- Brad


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
Rakesh Gulati
Sent: Monday, March 14, 2005 8:03 PM
To: sv-bc@eda.org
Cc: spsaha
Subject: [sv-bc] overiding the port of task



task t1 (output x);
  int x = 0;
 endtask

In the above example there is a error which can be classified into two 
categories

1. The port output x  has been declared in ANSI style and int x =0  is 
declared in task body
    in non  ANSI style, if int x =0 is not overriding the output port 
type then it should give
    an error for redeclaration of x. As there is no reference in LRM for 
overriding ANSI
     port by Non-ANSI port.

2.  If it is overriding the output port, then as per LRM output port 
cannot have default
     arguments,

Whether it is a positive testcase or not. If it is a negative testcase 
then what kind of
  error should be reported.

Thanks
Rakesh