RE: [sv-bc] Net declaration and implicit continuous assignment

Rakesh,

 

1.	There is only one instance of r, called p1::r, so the answer is
1. BTW, an import statement can only appear where it is legal to put a
data declaration, so you can't put the import in the middle of the
second initial block.
2.	You are correct that if you import a wire from a package in a
procedural block, you will not be able to write to it. However you can
put an import statement at the top level of a module or in $unit where
you can use a continuous assignment.

 

Dave

 

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Rakesh Gulati
Sent: Thursday, March 17, 2005 1:01 AM
To: sv-bc
Cc: spsaha; kaushik datta; Samiran Chattopadhyay
Subject: Re: [sv-bc] Net declaration and implicit continuous assignment

 

package p1;
  reg [3:0]r = 5;
 endpackage

module top;
  initial
     begin
        import p1::*;
         r = 1;
      end;
  
  initial
      begin
          reg [3:0]b;
          #5 b =2;
           import p1::*
           b = r;
      end
endmodule

1. A import syntax will make a variable declared in a package visible or
it is equivalent to declaration of package variables in a local scope.If
itmakes the variables visible then from above example if a package
variable is imported twice in diffrent scope it will be able to retain
the earlier changes  i.e  value of b will be 1.  If it is a declaration
then value of b should be 5. Please provide your suggesions.

Example 2;

package p1;
  wire a ;
 enpackage;

module top;
  initial 
     begin 
          reg r;
           import p1::*;
            r = a;
      end
endmodule
2. If we consider import syntax will make variables/nets visible, then a
net declared in a package can be used on the RHS of assignment. A net if
used on the RHS will have no significance untill it is driven by some
value. So if net should have some value package should allow declaration
for net as 
    wire A = varb & vara;   
which will be equivalent to continous assignment and hence illegal as
package cannot have any process.

If package import syntax will declare the package variables in a local
scope, then a net cannot be declared in procedural block. 
From above argument a net declaration is not a significant construct for
a package_or_generate_item_declaration. 

Please provide your suggestions for 1 &2 


Rakesh


Rich, Dave wrote:



Rakesh,
 
Packages are not supposed to contain any processes; therefore there
should be no continuous assignments. This may be an omission in the LRM.
 
Items in packages exist in the package, when the package is compiled.
Importing only makes the identifiers of the items visible in the scope
of where the import statement is placed.
 
Dave
 
 
  

	-----Original Message-----
	From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf
Of
	    

Rakesh
  

	Gulati
	Sent: Wednesday, March 16, 2005 5:03 AM
	To: sv-bc
	Cc: beacon-sv@cal.interrasystems.com; spsaha; vikas
	Subject: [sv-bc] Net declaration and implicit continous
assignment
	 
	 
	 
	  From System Verilog LRM 3.1 section  5.6
	 
	wire w = vara & varb   //continous assignment
	 
	 
	  From section 18.2
	 
	package_or_generate_item_declaration::=
	    net_declaration
	  | ...
	 
	Now considering the examples
	 
	Example 1
	 
	reg a,b;
	wire c = a&b;
	module top;
	  endmodule
	 
	Example 2
	 
	   package p1;
	      reg a,b;
	       wire c = a &b;
	   endpackage
	 
	  1. Will wire c = a&b   will be treated as continous assignment
	     in compilation unit scope ?
	 
	  2.  If a package is imported in a module scope(not in
procedural
	    

block)
  

	      then continous assignment will come into focus only after
the
	      import statment ?
	 
	  3. A package can be imported in a procedural block, if a
package
	    

with
  

	     implicit continous assignment is imported in a procedural
block
	    

it
  

	     will be error.How this behaviour will be handled ?