RE: [sv-bc] Net declaration and implicit continous assignment

 You cannot have a net with an continuous assignment declared in a package.
We should add a footnote to that effect in the bnf.
Francoise
    '


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Rakesh
Gulati
Sent: Wednesday, March 16, 2005 8:03 AM
To: sv-bc
Cc: beacon-sv@cal.interrasystems.com; spsaha; vikas
Subject: [sv-bc] Net declaration and implicit continous assignment



  From System Verilog LRM 3.1 section  5.6

wire w = vara & varb   //continous assignment


  From section 18.2

package_or_generate_item_declaration::=
    net_declaration
  | ...

Now considering the examples

Example 1

reg a,b;
wire c = a&b;
module top;
  endmodule

Example 2

   package p1;
      reg a,b;
       wire c = a &b;
   endpackage

  1. Will wire c = a&b   will be treated as continous assignment
     in compilation unit scope ?

  2.  If a package is imported in a module scope(not in procedural block)
      then continous assignment will come into focus only after the
      import statment ?

  3. A package can be imported in a procedural block, if a package with
     implicit continous assignment is imported in a procedural block it
     will be error.How this behaviour will be handled ?