RE: [sv-bc] Net declaration and implicit continuous assignment

 


  _____  

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Rakesh
Gulati
Sent: Thursday, March 17, 2005 4:01 AM
To: sv-bc
Cc: spsaha; kaushik datta; Samiran Chattopadhyay
Subject: Re: [sv-bc] Net declaration and implicit continuous assignment


package p1;
  reg [3:0]r = 5;
 endpackage

module top;
  initial
     begin
        import p1::*;
         r = 1;
      end;
  
  initial
      begin
          reg [3:0]b;
          #5 b =2;
           import p1::*
           b = r;
      end
endmodule

1. A import syntax will make a variable declared in a package visible or it
is equivalent to declaration of package variables in a local scope.If
itmakes the variables visible then from above example if a package variable
is imported twice in diffrent scope it will be able to retain the earlier
changes  i.e  value of b will be 1.  If it is a declaration then value of b
should be 5. Please provide your suggesions. 
 
r is like a shared declaration of which p1::r is a local reference to that
declaration, the value of p1::r wherever it is 
imported is the same as the value of r. Hence the value of p1::r in the
initial blocks is the value of r which has been
set to 1 in the first initial block. So b = 1 in the second initial block. 

Example 2;

package p1;
  wire a ;
 enpackage;

module top;
  initial 
     begin 
          reg r;
           import p1::*;
            r = a;
      end
endmodule
2. If we consider import syntax will make variables/nets visible, then a net
declared in a package can be used on the RHS of assignment. A net if used on
the RHS will have no significance untill it is driven by some value. So if
net should have some value package should allow declaration for net as 
    wire A = varb & vara;   
which will be equivalent to continous assignment and hence illegal as
package cannot have any process. 
 
You can drive the wire a outside the package and have continuous assignments
to a outside package p1:
module top
  import p1::*;
 assign a = ...;
 

If package import syntax will declare the package variables in a local
scope, then a net cannot be declared in procedural block.  
By importing the net in the procedural scope, you make the net visible, you
do not re-declared it. However the identifier of the net becomes a symbol of
that scope and you cannot declare another object of the same name. That is
the effect of the import: it acts as if it were a local declaration of the
imported item. 
>From above argument a net declaration is not a significant construct for a
package_or_generate_item_declaration. 

Please provide your suggestions for 1 &2 


Rakesh


Rich, Dave wrote:


Rakesh,



Packages are not supposed to contain any processes; therefore there

should be no continuous assignments. This may be an omission in the LRM.



Items in packages exist in the package, when the package is compiled.

Importing only makes the identifiers of the items visible in the scope

of where the import statement is placed.



Dave





  

-----Original Message-----

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of

    

Rakesh

  

Gulati

Sent: Wednesday, March 16, 2005 5:03 AM

To: sv-bc

Cc: beacon-sv@cal.interrasystems.com; spsaha; vikas

Subject: [sv-bc] Net declaration and implicit continous assignment







  From System Verilog LRM 3.1 section  5.6



wire w = vara & varb   //continous assignment





  From section 18.2



package_or_generate_item_declaration::=

    net_declaration

  | ...



Now considering the examples



Example 1



reg a,b;

wire c = a&b;

module top;

  endmodule



Example 2



   package p1;

      reg a,b;

       wire c = a &b;

   endpackage



  1. Will wire c = a&b   will be treated as continous assignment

     in compilation unit scope ?



  2.  If a package is imported in a module scope(not in procedural

    

block)

  

      then continous assignment will come into focus only after the

      import statment ?



  3. A package can be imported in a procedural block, if a package

    

with

  

     implicit continous assignment is imported in a procedural block

    

it

  

     will be error.How this behaviour will be handled ?