If you go way back to the original proposal from Cliff on Dec 13, 2001, at http://www.eda.org/vlog-pp/hm/0208.html, you will find these rules: * If a port on an instantiated sub-block is unconnected in the upper-level module, the port shall be explicitly listed as a named port with empty parentheses showing there is no connection to the port. * All nets or busses in the upper-level module that connect to implicit ports must either be explicitly declared as a scalar-net, vector-net, or as a port on the upper-level module. Shalom Mark Hartoog wrote: > > >So I hear agreement that the LRM says that when you use .*, > > every port > > >of the instance must end up connected unless it was listed as > > >unconnected in an explicit named connection. Otherwise you > > get an error. > > > > That's my recollection of the intent. See also section 3 of > > Cliff's recent DesignCon paper on SystemVerilog implicit port > > connections -- > > > > http://www.sunburst-design.com/papers/ > > > > -- Brad > > This was also my recollection of how this was intented to work. > > Mark Hartoog > 700 E. Middlefield Road > Mountain View, CA 94043 > 650 584-5404 > markh@synopsys.com -- Shalom.Bresticker @freescale.com Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential ProprietaryReceived on Sat Mar 26 22:33:24 2005
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