Re: [sv-bc] Pls Clarify: Expression Sizing and assignment operators.

Krishna,

That's my understanding, but it never hurts to be more explicit.
I think the type of the assignment expression is the type of its
left-hand side, and that a Verilog assignment always delimits an
independent type context.  (See also the definition of
assignment-like contexts, immediately after Syntax 8-2 in the
balloting draft.)

-- Brad

-----Original Message-----
From: Krishna Garlapati [mailto:krishna@synplicity.com]
Sent: Friday, March 25, 2005 4:47 PM
To: Brad.Pierce@synopsys.COM
Cc: sv-bc@eda.org
Subject: Re: [sv-bc] Pls Clarify: Expression Sizing and assignment
operators.




Brad, Thanks for your reply.

Does that mean, the size (not the type) of an assignment
expression is always context independent ?? In other words,
Is it always self-determined ??

The page you pointed out only talks about the types and it
mentions size only as a passing reference for concatenations.
I wish there was a line explicitly saying something like:

The size of an assignment expression is always self-determined.


- Krishna.


Brad Pierce wrote:
> The semantics of assignment expressions are described
> at the top of p.71 in the balloting draft.  Here's
> how I interpret them --
> 
>     a = b * (c+=3);
> 
> is
> 
>     a = b * (c=c+3);
> 
> is
> 
>     a = b * f(c,c+3);
> 
> where, for T==$typeof(c),
> 
>     function automatic T f(output T LHS, input T RHS);
>       LHS = RHS;
>       return LHS;
>     endfunction
> 
> The assignment to c is a context independent of the
> assignment to a.
> 
> -- Brad
> 
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
> Krishna Garlapati
> Sent: Friday, March 25, 2005 3:31 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] Pls Clarify: Expression Sizing and assignment
> operators.
> 
> 
> 
> I hope I am not raising something that has been discussed already.
> 
> Section 7.7, D4 says that SystemVerilog follows the same sizing
> rules as Verilog.
> 
> Consider:
> 
> a = b * (c+=3);
> 
> My question is: Does the size of the 2nd operand in the += assign
> expression (32 bits) effect the size of the full expression ??
> (I hope not)
> 
> I wish the LRM would specifically say a yes or no and explain it
> since this is unique to SystemVerilog.
> 
> 


-- 
Krishna
408-215-6152