Re: [sv-bc] FW: interpretation of priority if-else or case statement

Cliff,

>I have even seen one source recommend using either "priority"
>or "unique" with ALL  RTL case-statements and if-else-if-statements

And that's a good recommendation.  Here's my recommendation for
SystemVerilog case statements --

  1) Always use 'priority' or 'unique'.
  2) Always cover all reachable 2-state values.
  3) Always use a default X assignment.

Is the 'priority' keyword redundant if you remember to follow
rule 3?  Yes, but so are line breaks and indentation.

A fourth recommendation, to enforce rule 3 and to self-document
which variable is assigned by the case --

     `define PRIORITY_CASE(expr, lhs, assign) \
            priority case (expr) default lhs assign 'x ;

For example,

      `PRIORITY_CASE(expr, o, <=)
         2'b00: ...
         ...
       endcase

Likewise,

     `define PARALLEL_CASE(expr, lhs, assign) \
            unique case (expr) default lhs assign 'x ;

-- Brad