RE: [sv-bc] Action item: Update item 548

The SystemVerilog 3.0 LRM section 12.7.4 had the explicit rule:

- Implicit .* port connections cannot be used in the same instantiation
with implicit .name port connections.

This rule was deleted in the SystemVerilog 3.1 LRM because it was an
unnecessary restriction.

Now we have a solid reason for allowing it. So forget the rule ever
existed :)

Dave




> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven
> Sharp
> Sent: Friday, April 01, 2005 5:17 PM
> To: sv-bc@eda.org; Brad.Pierce@synopsys.com
> Subject: Re: [sv-bc] Action item: Update item 548
> 
> 
> >Moreover, I believe that .name and .* can't be used together
> >in the same instantiation.
> 
> That is what I remember from somewhere.  Dave has said that this
> restriction has been removed.  I can't seem to find it, even in my
> older drafts, so I can't confirm that.
> 
> Steven Sharp
> sharp@cadence.com