Re: [sv-bc] Action item: Update item 548

Hi, All -

The following was intended and can be added to the LRM if clarification is 
in order.

Add another paragraph to the end of section 19.11.3

It shall be illegal to mix .name implicit ports with positional ports in 
the same module instantiation.

Add another paragraph to the end of section 19.11.4

It shall be illegal to mix .* implicit ports with positional ports in the 
same module instantiation. It shall also be illegal to mix .name implicit 
ports and .* implicit ports in the same module instantiation.

If you read my DesignCon paper on SystemVerilog implicit ports, as 
referenced by Brad in an earlier discussion on .* implicit ports, I list 
these rules explicitly in section 3.

www.sunburst-design.com/papers/CummingsDesignCon2005_SystemVerilog_ImplicitPorts.pdf

When I made the .name and .* proposals, I could see no good reason to mix 
.name and .* in the same instantiation. About the only reason one would 
want to do this is if one wanted to implicitly connect all ports using .* 
and then document what one or two ports were that were also available in 
the module header and list those with .name connections (which is currently 
illegal or intended to be illegal). The .name and .* are overlapping 
capabilities where the first documents the ports when the module is 
instantiated and the second just says connect them up for me.

It is so much easier to just write a verbose paper with lots of examples 
and explanations of intent (like the one above) compared to offering 
concise, accurate specification-language.   ;-)

Regards - Cliff

At 04:25 PM 4/1/2005, Steven Sharp wrote:

> >The LRM explicitly says that it's legal.  See the last paragraph in 19.11.4.
>
>That paragraph has a problem.  If you assume that it means that these can
>be used in any combination in the same instantiation, then it says that
>it is legal to mix positional and named connections.  This is wrong.  You
>can use positional, or combinations of explicit or implicit named
>connections.  However, you cannot mix positional with named.
>
>The part of the sentence that says "into the same parent module" implies
>that it is talking about different instantiations in the same module.
>That means you can use positional in one instantiation and named in
>another, or implicit named in one and implicit .* in another.  It does
>not mean you can use positional and named in the same instantiation,
>and therefore it does not mean you can use implicit named and implicit
>.* in the same instantiation.
>
>So I disagree that this paragraph says it is legal, unless this paragraph
>is also saying that you can mix positional and named.  And if it is saying
>that, then it needs to be fixed.
>
>Steven Sharp
>sharp@cadence.com

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training