At the SV-BC on April 4th, issue 213 requested the ability to construct SystemVerilog identifiers from strings computed at runtime. I offer the following response: There are many features in SystemVerilog that eliminate the need to use strings to connect to design signals. e and Vera had to do this because they were separate languages that connected via the PLI. Besides being able to use hierarchical names directly in SystemVerilog, you can also pass signals by reference and use virtual interfaces which essentially give you pointers to signals. Generate statements can create iterated references to arrayed instances. There is also signal aliasing to group and ungroup bits of a bus. SystemVerilog has the VPI to do all sorts of programmable connections to the design, much more powerful than what you can do with simple strings. Even more powerful is the ability to access the VPI using the DPI to get built-in language introspection. Attached is a small but complete example that shows how easy it is to reference a signal name by string expression by using the VPI through the DPI. Dave David Rich Verification Technologist Design Verification & Test Division Mentor Graphics Corporation dave_rich@mentor.com Office: 408 487-7206 Cell: 510 589-2625
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