OLD: "In Verilog, an initialization value specified as part of the declaration is executed as if the assignment were made from an initial block, after simulation has started. Therefore, the initialization can cause an event on that variable at simulation time zero. In SystemVerilog, setting the initial value of a static variable as part of the variable declaration (including static class members) shall occur before any initial or always blocks are started, and so does not generate an event. If an event is needed, an initial block should be used to assign the initial values." NEW: "In Verilog, an initialization value specified as part of the declaration is executed as if the assignment were made from an initial block, after simulation has started. In SystemVerilog, setting the initial value of a static variable as part of the variable declaration (including static class members) shall occur before any initial or always blocks are started." Steven Sharp sharp@cadence.comReceived on Tue Apr 12 09:36:15 2005
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