[sv-bc] Proposal on striking the 2 paragraphs

Here's Doug's proposal.

>-----Original Message-----
>Subject: Proposal on striking the 2 paragraphs
>
>
>Team,
>
>I think this is a safe proposal to make regarding "events" at time 0.
>It doesn't "tighten up" specification of time zero behavior.
>However, it does remove possibly confusing and contradictory
>statements.
>
>OLD:
>In Verilog, an initialization value specified as part of the 
>declaration
>is executed as if the assignment were made
>from an initial block, after simulation has started. Therefore, the
>initialization can cause an event on that variable
>at simulation time zero.
>
>In SystemVerilog, setting the initial value of a static 
>variable as part
>of the variable declaration (including static
>class members) shall occur before any initial or always blocks are
>started, and so does not generate an event.
>If an event is needed, an initial block should be used to assign the
>initial values.
>
>NEW:
>In SystemVerilog, setting the initial value of a static 
>variable as part
>of the variable declaration (including static
>class members) shall occur before any initial or always blocks are
>started.
>
>***
>
>We'll have to add or modify other language to specify exactly which 
>combinational constructs execute at time 0.
>
>Regards,
>Doug
>
>