Dave Rich wrote: >This is why I say no one should be using always @ anymore when using >SystemVerilog. And as Steve pointed out, the implicit continuous >assignment created when someone connects to a legacy Verilog block will >create the necessary event that triggers the always block. I would agree with this argument if initializers had been first introduced in SystemVerilog. However, they were introduced in Verilog-2001. There may be initializers inside that legacy Verilog block that don't go through a port to reach that legacy always @ block. Steven Sharp sharp@cadence.comReceived on Tue Apr 19 14:54:42 2005
This archive was generated by hypermail 2.1.8 : Tue Apr 19 2005 - 14:56:03 PDT