>I believe in the Monday P1800 meeting we voted to ask 1364 to >add this into the 1364 LRM, because all real Verilog simulators >must be doing this, otherwise contassigns to constants would >not work >We thought this more correctly belonged in 1364 rather than P1800. Yes, we voted to send a recommendation to 1364 to add a requirement that continuous assignments and combinational primitives be evaluated at time 0, much like always_comb. A major reason for this is 2-state types in SystemVerilog, which do not start out at X. However, this is also needed in Verilog when such assignments or primitives have constant inputs. This would also resolve issues with initializers (order of execution and/or creation of events) where continuous assignments and primitives are concerned. It does not resolve these issues for combinational always blocks. Steven Sharp sharp@cadence.comReceived on Wed Apr 13 14:37:07 2005
This archive was generated by hypermail 2.1.8 : Wed Apr 13 2005 - 14:38:02 PDT