RE: [sv-bc] Proposal on striking the 2 paragraphs

I believe in the Monday P1800 meeting we voted to ask 1364 to 
add this into the 1364 LRM, because all real Verilog simulators
must be doing this, otherwise contassigns to constants would
not work:

wire w;
assign w = 0; // no event to trigger 

We thought this more correctly belonged in 1364 rather than P1800.


> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On 
> Behalf Of Shalom.Bresticker@freescale.com
> Sent: Wednesday, April 13, 2005 4:48 AM
> To: Rich, Dave
> Cc: sv-bc@eda.org
> Subject: RE: [sv-bc] Proposal on striking the 2 paragraphs
> 
> By the way, wearing my hat as a standards writer, if it is 
> not written in the LRM, then it does not exist. And if a tool 
> executes these constructs at time 0, then it is possibly 
> noncompliant to the written word of the LRM. The solution of 
> course is to change the LRM in this case, because the 
> execution at time 0 is REQUIRED to order to give the correct results.
> 
> Shalom
> 
> > > I think everyone whom I have heard an opinion is in 
> agreement that 
> > > all combinational constructs (continuous assignments, 
> combinational 
> > > primitives, etc) must all have executed at least once 
> before the end 
> > > of time 0.
> > 
> > So what is the problem to say explicitly that they execute 
> like always_comb?
> > In concept, they are exactly the same.
> > It is a problem if they will execute before initializers and then 
> > initalizers will not create events.
> > I agree that we can separate between 'always @' and the other 
> > combinational constructs.
> 
> -- 
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