At 10:56 AM 4/26/2005, Michael McNamara wrote: > Looking forward, most seem to agree from an engineering perspective > that keeping config blocks in their own file makes the most sense. > > (Quick Poll: does everyone agree to this?) Yes and No. Yes - from a methodology approach, I agree that it is generally good practice to keep configs in a separate file, and I will continue to teach this in my classes. No - There are times when a quick-test will throw a config, a simple testbench and a design module or two into the same file to test a concept. A requirement to build separate files for concept-testing is annoying. No - It is sometimes useful to put the configuration, testbench, and design files into a single file and send it to a colleague and tell them to just run the file with your Verilog simulator. It is also sometimes easy to package a problem to send to a vendor this way, instead of sending the tar-ball and Makefile. No - It is very useful to replace -v -y +libext+.v and some -f command line switches with configs, without the requirement to add different command line switches. Keeping configs in the Verilog input stream makes this possible. The context sensitive config idea does have merit. Separate email for that. Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification TrainingReceived on Tue Apr 26 11:54:05 2005
This archive was generated by hypermail 2.1.8 : Tue Apr 26 2005 - 11:54:44 PDT