Re: [sv-bc] Keywords

-- On Apr 26 2005 at 11:10, Kevin Cameron sent a message:
 > To: mac@verisity.com, cliffc@sunburst-design.com, sv-bc@eda.org
 > Subject: "Re: [sv-bc] Keywords"
 > Michael McNamara wrote:
 > 
 > >....
 > >
 > > Looking forward, most seem to agree from an engineering perspective
 > > that keeping config blocks in their own file makes the most sense.
 > >
 > > (Quick Poll: does everyone agree to this?) 
 > >
 > >  
 > >
 > No. Managing multiple files in an automated flow can get awkward, and it 
 > breaks the all-input
 > as a single-stream approach Verilog traditionally supports. I think it's 
 > a good idea to be able
 > to put a design in one (big) file even if you don't do it very often.
 > 
 > Kev.

Perhaps you missed this, but with an "all the design in one file"
approach, the config block is pretty much useless.  

What config allows you to do is tell the compiler to use the module
definition for "dff16" from the file that matches the pattern
"dff16*.v" from the directory "rtl" instead of the from the file that
matches the pattern "dff16*.vg" from the directory "gates".

If everything is in one file, then config is moot.

-mac