Hi, Brad - Thanks for finding this. At 03:03 PM 4/26/2005, Brad Pierce wrote: >According to > > http://boydtechinc.com/btf/archive/btf_1998/0243.html > >"EDA vendors" wanted to used 'config' instead of 'configuration', >as originally proposed, in order to "distinguish between Verilog >and VHDL configuration files". > >For example, Jay Lawrence in > > http://boydtechinc.com/btf/archive/btf_1998/0244.html > >writes > > "Thanks, it would make my life easier as a dual-language compiler > developer...." > >According to Steven, the 'config' keyword overlaps with identifiers >in real Verilog designs. > >Why not move back to 'configuration' as originally proposed and help >out the users at the expense of the compiler developers? > >-- Brad I know it is still open for debate, but I believe reading configs in the Verilog input stream is the correct behavior. There is now an actual problem with using "configuration." First, Verilog configs have inheritance and VHDL configurations do not. Second, I believe VHDL configurations do a couple of things that Verilog configs don't do. So now the mixed language vendors would have to sort that out inside of the configuration. I have learned that some VHDL engineers are actually using Verilog configs because of the simplicity of the syntax and the ease of use and inheritance in mixed-mode simulations. Changing the keyword config will actually impact those VHDL engineers! Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification TrainingReceived on Tue Apr 26 17:45:35 2005
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