[sv-bc] FW: BOUNCE sv-bc@eda.org: Non-member submission from [John Havlicek <john.havlicek@freescale.com>]

 

>-----Original Message-----
>Date: Wed, 4 May 2005 11:22:39 -0500
>Message-Id: <200505041622.j44GMdOq011509@cde-tx32-ldt270.sps.mot.com>
>To: cliffc@sunburst-design.com
>Cc: sv-bc@server.eda.org, sv-ec@server.eda.org, sv-ac@server.eda.org,
>        sv-cc@server.eda.org, tom_fitzpatrick@mentorg.com
>In-reply-to: 
><6.0.1.1.0.20050503092716.042dee38@mail.sunburst-design.com>
>	(cliffc@sunburst-design.com)
>Subject: Re: [sv-ac] Issue #266 - Rev 5
>From: John Havlicek <john.havlicek@freescale.com>
>
>Cliff:
>
>I have looked over your proposed changes for Section 18, and 
>they all look fine to me.  I did think that in the last of 
>them (18.15) it might be better to change 
>
>   This applies to both pre-existing names as well as instance names
>   introduced by other {\bf bind} statements; and the latter situation
>   will occur if the design contains more than one instance of a
>   module containing a {\bf bind} statement.
>
>to
>  
>   This applies to both pre-existing names as well as instance names
>   introduced by other {\bf bind} statements.  The latter situation
>   will occur if the design contains more than one instance of a
>   module containing a {\bf bind} statement.
>
>Best regards,
>
>John H.
>
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>> Date: Tue, 03 May 2005 09:29:10 -0700
>> From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
>> Cc: Tom Fitzpatrick <tom_fitzpatrick@mentorg.com>
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>> 
>> Subject: Issue #266 - Version 5 - May 3, 2005
>> 
>> We have passed Issue #266 in the following committees:
>> SV-BC
>> SV-EC
>> 
>> I have not received definitive feedback from the following 
>committees:
>> SV-AC
>> SV-CC (SV-CC action items below)
>> 
>> The Champions Committee will have one last opportunity to make 
>> additional changes before passing the proposed resolution on to the 
>> SystemVerilog main committee.
>> 
>> Regards - Cliff
>> 
>> ----------------------------------------------------
>> Cliff Cummings - Sunburst Design, Inc.
>> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
>> Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / 
>> www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and 
>> Verification Training
>> 
>