RE: [sv-bc] Naming of unnamed sequential blocks

> I believe Mark was mistaken is saying that unnamed blocks and 
> automatics can not be access form the VPI.

What I was trying to say is that automatic variables do not have 
allocated storage except when the block is active. I don't see
how waveform files could display automatic variables. VPI could
only give access to the values of automatic variables in blocks
that are currently active. 

I asked a VPI expert, who told me that automatic variables can be 
accessed in VPI through a VPI frame handle for active blocks, but 
automatic variables can never be accessed through the scope handle, 
even when the block is active. 

One issue you might want to think about is this Verilog 1995 code:

module test;
task t;
input x;
begin
    if (x) begin : blk
        reg y;
    end
end
endtask
initial $display(t.blk.y);
endmodule

The hierarchical name 't.blk.y' is perfectly valid. Now if I modify this 
design to System Verilog and add a variable in the enclosing unnamed block:

module test;
task t;
input x;
begin
    reg z;
    if (x) begin : blk
        reg y;
    end
end
endtask
initial $display(t.blk.y);
endmodule

Is the hierarchical name 't.blk.y' now illegal?

Mark Hartoog
700 E. Middlefield Road
Mountain View, CA 94043
650 584-5404
markh@synopsys.com