RE: [sv-bc] Naming of unnamed sequential blocks

An unnamed block does not create a scope based of my interpretation that
the LRM specifically states that a "named block creates a new scope" and
that backward compatibility with V2K is a given except if stated
otherwise.

The generated block name is only seen when asking for the fullname of
the variable declared in the unnamed block.

Dave


> -----Original Message-----
> From: Mark Hartoog [mailto:Mark.Hartoog@synopsys.com]
> Sent: Thursday, May 19, 2005 11:27 AM
> To: Rich, Dave; mac@verisity.com; stuart@sutherland-hdl.com
> Cc: Shalom.Bresticker@freescale.com; sv-bc@eda.org
> Subject: RE: [sv-bc] Naming of unnamed sequential blocks
> 
>
> 
> One issue you might want to think about is this Verilog 1995 code:
> 
> module test;
> task t;
> input x;
> begin
>     if (x) begin : blk
>         reg y;
>     end
> end
> endtask
> initial $display(t.blk.y);
> endmodule
> 
> The hierarchical name 't.blk.y' is perfectly valid. Now if I modify
this
> design to System Verilog and add a variable in the enclosing unnamed
> block:
> 
> module test;
> task t;
> input x;
> begin
>     reg z;
>     if (x) begin : blk
>         reg y;
>     end
> end
> endtask
> initial $display(t.blk.y);
> endmodule
> 
> Is the hierarchical name 't.blk.y' now illegal?
> 
> Mark Hartoog
> 700 E. Middlefield Road
> Mountain View, CA 94043
> 650 584-5404
> markh@synopsys.com
> 
>