RE: [sv-bc] Naming of unnamed sequential blocks

I don't think anyone disagrees with the need to standardize the
conventions for generating names of variables declared in unnamed
blocks. That should be an issue for the sv-cc. There is no way to use
those names from the source text.

But I disagree with the notion that the occurrence of declaring a
variable in an unnamed block creates a scope. Consider a 'for' loop with
a local declaration. I don't think users expect that to hide the nested
named blocks in the 'for' loop.

It's too late to debate whether it was a good idea to allow variables to
be declared in unnamed blocks. It will be in the IEEE-1800 standard. You
can choose not to implement it, and another PAR can remove it later.

Dave


> -----Original Message-----
> From: Krishna Garlapati [mailto:krishna@synplicity.com]
> Sent: Thursday, May 19, 2005 1:31 PM
> To: Steven Sharp
> Cc: Rich, Dave; mac@verisity.com; stuart@sutherland-hdl.com;
> Mark.Hartoog@synopsys.com; Shalom.Bresticker@freescale.com;
sv-bc@eda.org
> Subject: Re: [sv-bc] Naming of unnamed sequential blocks
> 
> 
> I agree with Steven Sharp. My personal opinion is that declarations
> should not be allowed in unnamed blocks. And, if declarations are
> allowed, the LRM should specify a naming convention that is consistent
> across the whole language.
> 
> Inconsistent naming has (and still is) been big problem here when a
> user runs equivalence check on the synthesis output and it fails due
> to a name mismatch.
> 
> - Krishna.
> 
> 
> Steven Sharp wrote:
> > Mark Hartoog wrote:
> >
> >>The hierarchical name 't.blk.y' is perfectly valid. Now if I modify
this
> >>design to System Verilog and add a variable in the enclosing unnamed
> block:
> >>
> >>module test;
> >>task t;
> >>input x;
> >>begin
> >>   reg z;
> >>   if (x) begin : blk
> >>       reg y;
> >>   end
> >>end
> >>endtask
> >>initial $display(t.blk.y);
> >>endmodule
> >>
> >>Is the hierarchical name 't.blk.y' now illegal?
> >
> >
> > In my opinion, yes.
> >
> > Declaring reg z is short-hand for naming the block and then
> > declaring reg z inside it.  You save the effort of naming
> > the block yourself, but give up the ability to refer to the
> > name.
> >
> > Steven Sharp
> > sharp@cadence.com
> >
> >
> >
> 
> 
> --
> Krishna
> 408-215-6152