Re: [sv-bc] Naming of unnamed sequential blocks

The reasoning for generate blocks was something like the following:

1. We needed these blocks to be scopes that the items are declared in.
2. We had a conflict between:
   a. Scopes in Verilog generally need to have names.
   b. Users don't want to have to provide an explicit name.
3. We resolved the conflict by borrowing what we understand to be the
   SystemVerilog definition for declarations in unnamed blocks:
   The blocks are scopes, but the compiler creates the name.  The
   user gives up the ability to reference any hierarchical path that
   would include that scope name.
4. We wanted consistent compiler-generated names between different
   implementations.  This costs nothing to specify, and ensures that
   tools produce the same names for VCD dumps, VPI applications, and
   user interfaces.
5. With consistent names, we could technically allow the user to
   reference the scope using its known generated name in the Verilog
   code.  However, the names are sensitive to changes made to the design,
   such as inserting new generate blocks before them, so this is a bad
   idea.  So we left it illegal to reference these names in hierarchical
   paths in the Verilog code.

My understanding was that this matched SystemVerilog declarations in
unnamed blocks, except that SystemVerilog did not specify what the
compiler-generated names should be.  There were other people in the
1364 group who were also involved with the SystemVerilog standard, and
I don't recall anyone disagreeing with that interpretation.

Assuming this interpretation, we get back to the question of whether
SystemVerilog should specify what the compiler-generated names should
be for these unnamed blocks.  The same basic arguments apply as for
unnamed generate blocks: it costs little to specify it, and it gives
some advantages in consistency across tools.

Steven Sharp
sharp@cadence.com