RE: [sv-bc] Structure literal using data type

Structure literals have to use the syntax of assignment patterns:
'{} 

I am not sure that your type:value assignment is legal.
See section 8.13.1 and 8.13.2


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Subhankar Ghosh
Sent: Friday, May 27, 2005 7:00 AM
To: sv-bc@eda.org
Subject: [sv-bc] Structure literal using data type

Hi,

   Is it the correct syntax to use structure literal?
   
    It seems to me vector or array type member assignment through structure
literal is not clear in SV LRM.

Thanks
Subhankar

module test (input in1, input bit [15:0] in2, output reg [7:0] out1);

  typedef struct {
        bit a[4:0];
        logic [7:0] b;
} my_struct;

my_struct struct_obj1;

always @(in1 or in2)
  begin
    struct_obj1 = {logic [7:0] : in2, bit : in1};
    out1 = struct_obj1.b;
  end

endmodule