Re: [sv-bc] expression width calculation

Yossi wrote:
>We had an issue here regarding the right semantic for:
>
>		wire a;
>		assign a = 4'b0101 == (signed' (3'b101));
>		
>Does 'a' equal 1 or 0?
>
>Can you please comment on our interpretation and make it clearer.

I am unclear myself on how casting works for the cases where the cast
is only a "partial type" (i.e. signing or width only).  In general,
casting is defined to be equivalent to assigning to a variable of
the casting type and then using the variable in place of the cast.
However, when the cast only specifies the signing, it is not clear
what the width of this conceptual variable is.  It could be the width
of the expression being cast, or the width of the context the cast
appears in.

The SV LRM says: 
"When changing the signing, the size passes through unchanged."

I am guessing that this was intended to mean that the result of the
cast has the size of the expression being cast, i.e. 3 bits.  However,
it is a very bad way of saying it, given how Verilog expression widths
are determined.  It was probably written with the mistaken idea that
sizes only pass upward.  Since Verilog passes the size of an expression
back down to the context-determined operands to determine their size,
it could be interpreted as meaning that the size passed upward (3 bits)
is passed upward unchanged, and then the size passed back downward
(4 bits) is also passed through unchanged, so the value is extended to
4 bits before being cast.  I doubt that this was the intention.

I can give you a definite answer for your interpretations of the
Verilog LRM, without the SystemVerilog cast.  If we assume that the
result of the cast is 3 bits signed, equivalent to 3'sb101, then the
answer is that (4'b0101 == 3'sb101) will be 1.  I believe this matches
your interpretation.


>The question that we ask is in fact: does the width-extension of the
>constant happen before the signed-cast was applied or after. The
>standard is not clear enough on the topics related to calculation of
>expression widths. 

I agree that this is the fundamental question here.


>Base on Yulik's observations, we tend to use the following reasoning
>(which is not 100% clear) in this case:
> 
>*         According to Verilog's 5.5.2 "Steps for evaluating an
>expression", one should first determine expression type (size and sign)
>and then propagate it down to context-determined operands.
>*         The propagation stops when it reaches a "simple" operand (a
>"primary" in BNF). A cast is a simple operand, according to the
>definition of "primary" in SV BNF. Since the cast is a simple operand,
>we need to convert the type and size of the cast expression itself, not
>its operand. 

This seems like a reasonable argument, and matches my guess.


>*         After propagation stops, the operand is converted to the
>propagated type and size. If the operand is extended, it is
>sign-extended only if the propagated type is signed. 
>*         The cast expression has an "initial" size of 3 and it is
>signed (to my understanding). Now we need to convert it to the
>propagated type. The question is what is the propagated type?
>*         According to the 5.5.2 section, equality operands are neither
>fully self-determined nor fully context-determined. Their operands
>should affect each other as if they were context-determined operands
>with a result type and size determined from them. The size is chosen as
>the maximum of the two operand sizes, so the resulting size is 4.
>However, nothing special is said how the signing should be chosen in
>operands of equality operators.
>*         According to 5.5.1, for non-self-determined operands (and the
>operands of equality operators are not self-determined), if any operand
>is unsigned, the "result" is unsigned, regardless of the operator. If we
>assume that this "result" is the resulting type that should be
>propagated down the equality operands, then the resulting type should be
>unsigned, since the left operand is unsigned. This is another weak part
>of this reasoning.

Your reasoning on this is correct.  This is the intended interpretation
of that text in the Verilog LRM.  Note that this section in the LRM uses
the term "type" mostly to mean the signing, so when 5.5.2 says "with a
result type and size determined from them", it is saying how the signing
should be chosen.


>*         Based on the above, the type propagated to the cast expression
>from above is unsigned array of 4 elements, and the "initial" type of
>the cast expression is signed array of 3 elements. The cast expression
>should be extended, since 4 > 3. It should not be sign extended, since
>the propagated type is unsigned. Therefore zero-extension should be used
>(this is the case in Synopsys-DC).

If the assumptions about how this signed' cast works are correct, then
this is the correct answer.


Steven Sharp
sharp@cadence.com