RE: [sv-bc] Is an unnamed block with declarations a scope?

> Behalf Of Gordon Vreugdenhil
> 
> The three options I see are:
>    1) unnamed block is always a real scope
>    2) unnamed block is a real scope iff the block_item_declaration
>       list is empty
>    3) unnamed block is only a real scope for block_item_declaration
>       list elements (i.e. other labels go into the nearest upwards
>       named scope).
> 
> (1) is the only choice that breaks 1364 compatibility which 
> is why I was assuming that (1) was not the intent.  This 
> leaves me with either (2) or (3).  While both of those have 
> issues, I think that (2) is a cleaner rule with more obvious 
> effects and interactions.
> 
> Gord.
>

I believe that the superlog simulator implemented 3, but the SV and 
P1800 LRM are unclear about this. Choice 2 is simpler to implement
and understand.

A related issue to this is the naming of unnamed scopes. Even if you
cannot use heirachical names to access variables in unnamed blocks,
they still might appear in dump files and wave form displays, where
they need to be given a unique name. I think this can be accomplished
by just making up names for the unnamed scopes, similar to what is
done for unnamed generate blocks. I'm not sure it is an important
issue to standardize that naming convention across tools. 

Mark Hartoog
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