[sv-bc] Package Questions

Hi, All -

A reply to sv-bc@eda.org is good enough. I will follow the thread there.

(1) Can one declare extern task and extern functions in a package? A tried
to follow the BNF for the answer and I think I found a BNF-thread that
wound its way through some type of class-item to make this legal, but
thought I would ask the group.

(2) Can a package with useful typedefs be wildcard-imported (or even
specific pkg::typedef imported) before it is needed for ANSI-style ports?
Do I have to use Verilog-1995 style ports in order to get a package
imported before the typedefs are referenced?

(3) Is the group of the general opinion that we are moving away from
$root/$unit global typedefs and task/function declarations in favor of
packaged and imported copis of the same? (Methodology-opinion question)

Thanks for your thoughts.

Regards - Cliff