RE: [sv-bc] Package Questions

Hi Cliff,

Comments below

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Cliff
> Cummings
> Sent: Thursday, August 11, 2005 8:53 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] Package Questions
> 
> Hi, All -
> 
> A reply to sv-bc@eda.org is good enough. I will follow the thread
there.
> 
> (1) Can one declare extern task and extern functions in a package? A
tried
> to follow the BNF for the answer and I think I found a BNF-thread that
> wound its way through some type of class-item to make this legal, but
> thought I would ask the group.
[DR>] If you mean out of class-body declarations, they have to be
declared in the same scope as the class. You couldn't declare a class,
and then import its extern definitions. 
> 
> (2) Can a package with useful typedefs be wildcard-imported (or even
> specific pkg::typedef imported) before it is needed for ANSI-style
ports?
> Do I have to use Verilog-1995 style ports in order to get a package
> imported before the typedefs are referenced?
[DR>] Use import in the $unit scope
> 
> (3) Is the group of the general opinion that we are moving away from
> $root/$unit global typedefs and task/function declarations in favor of
> packaged and imported copis of the same? (Methodology-opinion
question)
[DR>] I think both methods can be useful. It depends on the visibility
requirements. $unit was created as a local $root and is like compilation
units in C. Certainly, you can always use a package where you could have
used $unit, but not the other way around.
> 
> Thanks for your thoughts.
> 
> Regards - Cliff