Hi, All - NOTE: it would be useful to have a semaphore.num() method to query how many keys are in the bucket. Use models: Since processes can put more keys back into the bucket that they have removed, interesting use models include: (1) Do not "put" any semaphore keys into the bucket until after simulation has started to delay execution of all semaphore processes. (2) Half-way through a simulation, put more keys into the bucket to get more processes running simultaneously. I have attached a few interpretations with examples. I now believe that semaphores were intended to behave the way Jamie outlined, but I think this needs to be quickly clarified and approved by the 1800 subcommittees and working groups. I can support this behavior because it sounds like this was the behavior of Vera and I see no reason to surprise former-Vera users with a new behavior for a known syntax. I believe I can also get the strict FIFO behavior by using the repeat command when I do a "get()". We need to clarify this ASAP. I have already taught more than 100 engineers the "wrong" way that semaphore get() works (I hate it when I do that!) Plus there is the interesting question that I do not believe has been answered yet, nor well documented, even though I think I know what the answer will be (the FIFO description can cause great confusion). Question: What will happen if there are no keys, process-A requests two keys (is put on the requesting FIFO) and later process-B requests one key? Is process-B put on the requesting FIFO behind process-A?? If one key is returned, does process-B come off the not-so-FIFO and become active?? I can live with Jamie, Arturo and Neil's interpretation of semaphores, but the LRM wording is clearly inadequate to describe this behavior. Please review the attached examples for accuracy (examples are not tested). Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training
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