RE: [sv-bc] Defparam on member of parameter struct

However, the statement

"The defparam statement is particularly useful for grouping
all of the
parameter value override assignments together in one module."

is still true.

Similar to the way we have lists of `defines.

Shalom


>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
>Behalf Of Clifford E. Cummings
>Sent: Monday, November 07, 2005 10:56 PM
>To: sv-bc@eda.org
>Subject: Re: [sv-bc] Defparam on member of parameter struct
>
>Most disappointing that we did not get this editorial opinion
>removed from
>the 2005 Standard.
>
>In my 2002 paper, section 6.6, down-loadable from
>www.sunburst-
>design.com/papers/CummingsHDLCON2002_Parameters.pdf
>
>I recommended the following:
>
>After defparams have been deprecated, the author
>suggests that future Verilog tools report errors whenever a
>defparam statement is found in any Verilog source code
>and then provide a switch to enable defparam statement
>use for backward compatibility. An error message similar
>to the following is suggested:
>
>"The Verilog compiler found a defparam
>statement in the source code at
>(file_name/line#).
>To use defparam statements in the Verilog
>source code, you must include the switch
>+Iamstupid on the command line which will
>degrade compiler performance and introduce
>potential problems but is bug-compatible
>with Verilog-1995 implementations.
>Defparam statements can be replaced with
>named parameter redefinition as defined by
>the IEEE Verilog-2001 standard."
>
>Grouping defparams into a separate file is one of the abuses
>that came into
>existence with defparams.
>
>In my discussions with Shalom, about the only reasonable use
>for the
>deprecated defparam is to change parameters hierarchically-down
>from the
>current module without the need to pass the parameter through
>multiple
>levels, which is what I currently advocate.
>
>A future extension to SystemVerilog might permit downward
>hierarchical
>named parameter passing, of the form:
>
>alu #(.u1.SIZE=8) alu1 (.*);
>
>Where u1 is an instance instantiated inside of the alu1
>instance of the alu
>module, and SIZE is a parameter inside of the u1-instantiated
>module.
>
>Regards - Cliff
>
>At 09:07 AM 11/7/2005, Brad Pierce wrote:
>>According to 12.2.1 of Verilog-2005 --
>>
>>   "The defparam statement is particularly useful for grouping
>all of the
>>parameter value override assignments together in one module."
>>
>>-- Brad
>>
>>
>
>----------------------------------------------------
>Cliff Cummings - Sunburst Design, Inc.
>14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
>Phone: 503-641-8446 / FAX: 503-641-8486
>cliffc@sunburst-design.com / www.sunburst-design.com
>Expert Verilog, SystemVerilog, Synthesis and Verification
>Training