RE: [sv-bc] Named blocks conflicts with existing identifiers

>Any "deferred" bindings in Verilog 2005 are treated in the same
>manner as hierarchical references and must have dotted names.
>Any undotted name can be resolved directly (other than the
>function/task/scope name issues that have already been noted).

[Yulik] I'm not sure how you can know whether you may resolve the given
identifier directly or you have to defer its resolution. Until you
resolve it, you don't know whether it is a function/task or other
"problematic" construct. Also, a non-hierarchical identifier
("undotted") may appear to be a cross-hierarchical reference, once you
resolve it. So, once again, it is not clear how one can decide whether
it will be OK to resolve the identifier before the hierarchy is
established.