Re: [sv-bc] Named blocks conflicts with existing identifiers

Feldman, Yulik wrote:
>>Any "deferred" bindings in Verilog 2005 are treated in the same
>>manner as hierarchical references and must have dotted names.
>>Any undotted name can be resolved directly (other than the
>>function/task/scope name issues that have already been noted).
> 
> 
> [Yulik] I'm not sure how you can know whether you may resolve the given
> identifier directly or you have to defer its resolution. Until you
> resolve it, you don't know whether it is a function/task or other
> "problematic" construct. 

Actually, you do.  Task/function calls are known to be so directly due
to parentheses.  This was in fact an issue in the initial P1800
work where unparenthesized calls were permitted even for functions
with simple names.  Due to the issues I am raising here, it was
recognized that this would intefere with implicit net creation and
the P1800 rules (see 12.4.5) were changed so that a compiler could
make correct assumptions.

 > Also, a non-hierarchical identifier
> ("undotted") may appear to be a cross-hierarchical reference, once you
> resolve it. 

Don't thnk so.  Not unless it is a scope reference (function, task, etc) which
are all in known contexts.

Can you give a definite example for a simple identifier that doesn't
name a scope/task/function of where you believe that this can happen?


 > So, once again, it is not clear how one can decide whether
> it will be OK to resolve the identifier before the hierarchy is
> established.

Gord.

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com