RE: [sv-bc] packed array question

>From: "Rich, Dave" <Dave_Rich@mentor.com>

>Someday, maybe long after we've all retired, we'll figure out a way to
>represent an integer without having to implement it as binary bit
>vector.

There are ways of doing this that are used in specialized applications.
However the Verilog LRM pretty much states that integers are represented
as binary (4-state) bit vectors in 2s-complement notation.

Since this isn't really a big deal, the most important thing is
presumably to make sure that the LRM says what was intended.  That
means adding the 'time' type to the list, and making sure that it
is clear enough that the restriction applies to synonyms for those
types.

Steven Sharp
sharp@cadence.com