Re: [sv-bc] packed array question

>You can still do
>
>bit [4:0][31:0] i;

But, according to the current BNF you can't do --

   bit [4:0] signed [31:0] i;

The BNF would make more sense as --

  packed_dimension ::=
      [ signing ] '[' constant_range ']'
   |  [ signing ] unsized_dimension

Signedness should be an attribute of a dimension.  Unlike VHDL,
SystemVerilog does not yet support multidimensional arrays (the ones
that can be unconstrained in more than one dimension), but only arrays
of arrays (the ones that can only be unconstrained in the
slowest-varying dimension).

-- Brad