Re: [sv-bc] Struct/array assignment pattern

Surya Pratik Saha wrote:
> Hi,
> In IEEE 1800 LRM, sec 8.13.1 specifies syntax/semantics of array assignment
> patterns. Does it apply only on unpacked array, or packed unpacked both? All the
> e.g. specified there used unpacked array. So I am bit confused. Is the following
> e.g. valid?

Surya,

    8.13.1 applies to all arrays.
"Simple bit vectors" are specially considered in those rules - to make
it easier to write "singular" values for array elements.  Because Verilog
concatenation syntax and assignment pattern syntax are so similar, early
implementations tried unsuccessfully to unify the syntax on this point.

   Your example uses "{}" twice where I think you expect an assignment
pattern rather than concatenation.  In both cases, the LRM would
require "'{", not "{".  Prototype implementations might accept the
code as you've written it: many ideas were tried but few were chosen.

Both of your assignment patterns work if you write them using '{...}.

> typedef bit [2:0] bit_array;
> 
> module sample;
>   bit_array [3:0] a;
> 
>   initial
>     a = { bit_array: {1, 1, 1}};

       a = '{ bit_array: '{1,1,1} };

This also "works" using LRM rules when written as:

       a = '{ bit_array: {1, 1, 1} };

But in this case the inner curlies become concatenation (yielding
a 96-bit vector) which gets truncated to 3'sb001.  Adding the '
takes advantage of the assignment-like context of "bit_array:"
to turn it into an assignment pattern.

Accellera SV 3.0 and 3.1 _did_ try to fit both features into {} syntax, and
they _did_ use packed vs unpacked to distinguish the two behaviors.
Some Synopsys products support those early dialects.  This may be the
source of your confusion. Assignment patterns moved to the '{} syntax
late in the process.

Use '{} vs {} to syntactically indicate which type of semantic behavior
you expect from the compiler.  The committee considered it harmful to
let this depend upon data type and complicated rules for resolving
ambiguous situations.  The extra ' seems ugly at first, but I'm getting
used to it now.

> endmodule

Just as a point of style, making packed {arrays, structs, or unions}
out of user-defined typedefs constrains the set of acceptable
definitions for the typedef.  Packed things can only contain other
packed things.  Your code would be more flexible if you did NOT do this.

Greg Jaxon

Disclaimer:  This post discusses the P1800 System Verilog standard,
not any particular Synopsys product.