Re: [sv-bc] Struct/array assignment pattern

>From: Greg Jaxon <Greg.Jaxon@synopsys.com>

One minor correction to Greg's reply (which was otherwise good):

>This also "works" using LRM rules when written as:
>
>       a = '{ bit_array: {1, 1, 1} };
>
>But in this case the inner curlies become concatenation (yielding
>a 96-bit vector) which gets truncated to 3'sb001.  Adding the '
>takes advantage of the assignment-like context of "bit_array:"
>to turn it into an assignment pattern.

This would actually be illegal, since unsized literals are not
allowed in concatenations in Verilog.  There has been debate over
whether this restriction is a good idea, but this is an example
where it may protect you from a mistake.  If you didn't realize that
each of these literals was 32 bits (or actually, an implementation-
defined size that is 32 bits or more), you might expect that the
concatenation would end up assigning 3'b111 instead of 3'b001.

(And an even more minor correction: it is not 3'sb001, since the
result of a concatenation is always considered to be unsigned, even
when all the operands are signed.)


Steven Sharp
sharp@cadence.com