RE: [sv-bc] compiler directives in middle of statement

>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>The following are 'interesting' cases:
>
>- sv, unlike Verilog, allows all sorts of code outside modules. 

I agree that there is potential for problems here.  Some directives
were required to appear outside of modules to prevent certain problems
from occurring.  When SV started allowing code outside of modules,
I doubt that anyone carefully considered the impact of that code
now potentially being interspersed with these directives.


Steven Sharp
sharp@cadence.com