[sv-bc] Selects use self-determined evaluation, but does it say so in LRM?

I don't find in the LRM that in v[E1], v[E2:E3], v[E4+:E5], and
v[E6-:E7] the expressions E1,..,E7 are evaluated in their
self-determined contexts.  For example,

 

module test(test_bit); // should be 1

output test_bit;

 

  wire [-4:3] w = 3'b111;

 

  `define M 2'b01 << 2 >> 2

  wire [2:0]              t   =   `M ;

  assign test_bit = w[t] != w[`M];

 

endmodule

 

-- Brad

 

 

 

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