RE: [sv-bc] areas for future work

  

Shalom,

I would hope that you have specific requirements that need to be
addressed. Most people have moved away from using dynamic timing
analysis because it is not accurate enough. And people are now beginning
to replace gate-level simulation with formal equivalence checking

Section 30 of the 1800 LRM is supposed to replace the need for a text
VCD file, which should eventually be deprecated.

Dave

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Tuesday, January 10, 2006 11:52 PM
To: sv-bc@eda.org
Subject: [sv-bc] areas for future work

 

Hi,

 

There are a few areas in Verilog/SystemVerilog which were not dealt with
very much in both 1364-2005 or 1800-2005, in terms of errata, clarity
and/or enhancements.

The ones which first come to mind are:

-         specify blocks/timing checks: all of errata, clarity, and
enhancements. Nearly everywhere we looked, we found problems here. And
new data types require enhancements. The problem is that most SV-BC
people probably are not well versed in these areas. Either 1800 should
create a new sub-committee for it or SV-BC should create a task force
for it. But we need to find people who are both well-versed in it and
have time and ability to do standards work.

-         UDPs: enhancements. I don't know whether this needs anything,
but we could probably find useful things.

-         VCD: enhancements. With new data types, this is badly out of
date.

Thanks,

Shalom

Shalom Bresticker

Intel Jerusalem LAD DA

+972 2 589-6852

+972 54 721-1033

I don't represent Intel