RE: [sv-bc] areas for future work

>Subject: RE: [sv-bc] areas for future work
>Date: Thu, 12 Jan 2006 09:33:28 -0700
>Thread-Topic: [sv-bc] areas for future work
>Thread-Index: AcYWg93v3+7qEdI/RAWJkKc6bYXqNQBDY8+gAADYEpA=
>From: "Premduth Vidyanandan" <premduth.vidyanandan@xilinx.com>
>To: "Rich, Dave" <Dave_Rich@mentor.com>,
>        "Bresticker, Shalom" <shalom.bresticker@intel.com>,
>        <sv-bc@server.eda.org>
>
>Hi Shalom,
>
>
>This may apply a lot in the ASIC world, although in the world 
>of FPGAs we are still asking customers to use timing 
>simulation. There are some aspects that formal verification 
>and static analysis by itself cannot cover. In our models the 
>most common one is block ram collisions in the Dual Port 
>memories, this can only be seen in timing simulation and thus 
>we ask people to run timing simulation still. In the last 
>DVCON I actually co-presented a paper on this as well.
>
>Our recommendation is do both timing simulation as well as 
>static timing analysis for FPGA designs.
>
>I can see the need to deprecate the text VCD file due to the 
>size problems, although I do not think that it should be done 
>for the sole purpose of not needing timing simulation. Xilinx 
>also uses this VCD file for power estimation so the decision 
>to deprecate this can put us in a lot of trouble.
>
>
>Thanks
>
>Duth
>