Re: [sv-bc] illegal priority if

It means that if the tool finds such a sequence, then a warning is not required.  So the tool is not required to prove whether the unique if is legal, but the tool is required to do some due diligence.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of francoise martinolle
Sent: Thursday, January 12, 2006 10:49 AM
To: 'Bresticker, Shalom'; sv-bc@eda.org
Subject: RE: [sv-bc] illegal priority if

 
I do not understand what it means "interleaving evaluation and *use* of the
conditions".
Also what is the meaning of the sentence "unless it can demonstrate a legal
interleaving so that no more than 
one condition is true"?
Does it mean that if I found 1 sequence of evaluation of each condition in
the branches that
does not make more than one condition true, the unique if is correct?

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Thursday, January 12, 2006 8:20 AM
To: sv-bc@eda.org
Subject: [sv-bc] illegal priority if

Question:

1800 10.4 says, 

"A unique if shall be illegal if, for any such interleaving of evaluation
and use of the conditions, more than one condition is true. For an illegal
unique if, an implementation shall be required to issue a warning, unless it
can demonstrate a legal interleaving so that no more than one condition is
true."

What is the meaning of this "illegality"?

Generally, "illegal" means a fatal compile-time error or something similar.
Is that really the meaning here? Or is the meaning simply that a warning (or
error, for strict people) message needs to be issued? 

I hope my question is clear.

Thanks,
Shalom


Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
+972 54 721-1033
I don't represent Intel